1. Field of the Invention
The present invention relates to a BIST (built in self-test) circuit having a pattern generator, an address generator and a result comparator for performing an operational test of a memory, a semiconductor integrated circuit provided with the BIST circuit, a design device of the BIST circuit and a test method of a memory.
2. Description of Related Art
In order to facilitate a test of a system LSI (Large Scale Integration) internal circuit such as a RAM (Random Access Memory) block, a built in self-test (BIST) for performing such test by a circuit itself included in the LSI is used. This is the technique of embedding a pattern generator, an address generator and a result comparator in a chip. In generation of a test pattern, algorithm called marching or checkerboard is often used. In a memory BIST, a memory can be tested by reading out data written to the RAM block and comparing the result. As a semiconductor integrated circuit mounted with a BIST circuit of a related art, the following circuits are known.
FIG. 23 is a block diagram showing a semiconductor integrated circuit disclosed in Japanese Unexamined Patent Application Publication No. 2000-163993 (Sakamoto). As shown in FIG. 23, the semiconductor integrated circuit disclosed by Sakamoto includes 2 memory circuit units 161 and 162 with different configuration of data bit width and address bit width and one BIST circuit 105 for performing a test of the memory circuit units 161 and 162. An address each with specific bit width, access signal and a refresh signal are independently connected to the memory circuit units 161 and 162 from the BIST circuit unit 105, test data generated in the BIST circuit unit 105 is connected to the memory circuit units 161 and 162 by the same data input line, and data read out from the memory circuit units 161 and 162 is connected independently to the BIST circuit unit 105 by a data output line each with specific bit width.
The memory circuit unit 161 includes a memory circuit 121, an address access signal multiplex 111 and a data multiplex 131. The memory circuit unit 162 includes a memory circuit 122, an address access signal multiplex 112 and a data multiplex 132. The memory circuit unit 162 differs from the memory circuit unit 161 in the structure of data bit width and address bit width.
An address access signal generation circuit 102 of the BIST circuit unit 105 has an address bit width which can generate an address value of the larger one in the maximum address value of the memory circuit units 161 and 162 and is able to generate the same address and access signal to the memory circuit units 161 and 162. A data generation circuit 103 can generate a data bit width of the larger one in the memory circuit units 161 and 162 and generates the same test data to the memory circuit units 161 and 162.
The memory circuit unit maximum address memory circuit 106 stores the maximum address value of the memory circuit units 161 and 162 respectively. The address determine circuit 107 determines that an address generated by the address access signal generation circuit 102 is more than the address set by the memory circuit unit maximum address memory circuit 106 for each of the memory circuit units 161 and 162 and independently generates a refresh operation signal of the memory circuit units 161 and 162.
Address access signal control circuits 181 and 182 respectively disable the address and the access signal generated by the address access signal generation circuit 102 by the refresh operation signal of the memory circuit units 161 and 162 which is generated by the address determine circuit 107. Refresh generation circuits 191 and 192 respectively generate a refresh signal of the memory circuit units 161 and 162 by the refresh operation signal of the memory circuit units 161 and 162 generated by the address determine circuit 107. Comparison circuits 141 and 142 respectively compare read-out data of the memory circuit units 161 and 162 with expected values generated by the data generation circuit 103 and output a result at an enable time and output a matching result at a disable time.
Data comparison signal control circuits 143 and 144 respectively disable the comparison circuits 141 and 142 of the memory circuit units 161 and 162 by the refresh operation signal of the memory circuit units 161 and 162 generated by the address determine circuit 107. The BIST control circuit 101 controls the address access signal generation circuit 102, the data generation circuit 103 and the data comparison signal control circuits 143 and 144 according to a test algorithm, tests the memory circuit units 161 and 162 and outputs an existence of an error in the memory circuit units 161 and 162 from the comparison result returned by the comparison circuits 141 and 142.
In this way, one BIST circuit 105 is shared by a plurality of memories (DRAM) 121 and 122 with different size. Address access of each memory 121 and 122 is controlled by the address determine circuit 107 using the maximum address memory circuit 106 for storing the maximum address of each memory 121 and 122. When testing the memories 121 and 122 in parallel, if distinguished as a nonexistence address in a certain memory, address access and an output comparison are disabled and a refresh signal is sent to the memory to stop the test operation.
FIG. 24 is shows a semiconductor integrated circuit disclosed in Japanese Unexamined Patent Application Publication No. 2000-111618 (Ida). As shown in FIG. 24, a BIST circuit disclosed by Ida tests 16 bits×16K word memory 202B and 8 bits×1K word memory 202C. The BIST circuit is mounted to the same LSI as the memories 202B and 202C and includes a BIST sub circuit 201 and 2 data input circuits 204 and data output circuits 205 that each of them corresponds to the memories 202B and 202C.
The BIST sub circuit 201 outputs representative 1 bit data to 2 data input circuits 204. The BIST sub circuit receives representative 1 bit data and degenerate 1 bit data from the 2 data output circuits 205 and transmits address signals 220 and a control signal group to 2 memories 202B and 202C. This transmission is performed through a bus 230, and in response to a select signal, a decoder circuit 203 outputs an enable signal to only one of the 2 memories 202B and 202C in order to activate.
The data input circuits 204 are provided to each of the memories 202B and 202C and generate positive phase test bit data and negative test bit data from representative 1 bit data 213 input from the BIST sub circuit 201 to write to the corresponding memory. The total number of bits of test bit data 216 is equal to the number of bits per word of the corresponding memory. Therefore, it is 16 bits for the memory 202B and 8 bits for the memory 202C.
The data output circuits 205 are also provided to each of the memories 202B and 202C and read out test bit data 218 corresponding to the test bit data 216 from the corresponding memory. Then, degenerate 1 bit data 215 is generated and output to the BIST sub circuit 201. This degenerate 1 bit data 215 indicates a difference of the representative 1 bit data 213 from the test bit data 218.
When receiving representative 1 bit data, the BIST sub circuit 201 can test the memories 202B and 202C by comparing with the representative 1 bit data 213 from the difference. Moreover, when receiving the degeneration 1 bit data 215, the BIST sub circuit 201 can test the memories 202B and 202C by knowing the difference from representative 1 bit data according to whether it is “1” or “0”.
As described above, in the BIST circuit disclosed by Ida, for a plurality of memories 202B and 202C with different size, the portion that can be shared as a test circuit is packed as the BIST sub circuit 201 and the test data input circuits 204 and the output circuits 205 which are specific to each memory are prepared separately. Moreover, the decoder 203 is provided to select each memory to test in serial.
FIG. 25 is a block diagram showing a semiconductor integrated circuit disclosed in Japanese Unexamined Patent Application Publication No. 2002-358797 (Yoshizawa). As shown in FIG. 25, a BIST circuit disclosed by Yoshizawa includes an address generator 303, a test mode control & data generator 301, a RAM interface block 309 and a comparator 310.
The test mode control & data generator 301 controls test mode and generates test data. The test mode controller 301 inputs a clock, a reset (RST) and a test mode switching signal and outputs a test mode signal, a data signal, an ascending/descending order specification signal and a last value.
The test mode switching signal is created by a logical sum taken by an OR gate 302 between a count stop signal 308a and an address counter initializing signal 312 that are output by the address generator 303. The address generator 303 inputs a CLK, a RST, the address counter initializing signal 312, a test mode signal 319, an ascending/descending order specification signal 301b output from the test mode controller 301, an address last value specification signal (last value) 301a and a count trigger signal 301d and outputs a X address (row address) and a Y address (column address).
The RAM interface block 309 inputs a X address 318, a Y address 317, a test mode, data, a CLK and a RST and outputs RAM input command address input data corresponding to the interface specification of a RAM to be tested from these inputs.
The comparator 310 compares testing RAM output data with expected value data (data) and outputs the comparison result. The address generator 303 is formed by an address counter 304, an address modulation circuit 305, a testing subarray specification circuit 306, an address scrambler 307 and a count last value detection circuit 308.
An address counter 304 inputs the RST, the count trigger signal 301d, the ascending/descending order specification signal 301b, and the count stop signal 308a output from the count last value detection circuit 308 and outputs an address (counter) count value 304a. 
The count last value detection circuit 308 inputs the last value 301a output from the test mode controller 301 and the count value 304a output from the address counter 304 and, outputs the count stop signal 308a. 
The address modulation circuit 305 inputs the address (counter) 304a output from the address counter 304, the test mode signal 319 and a modulation control from the test mode controller and outputs an (modulated) address 305a. The testing subarray specification circuit 306 inputs the (modulated) address 305a output from the address modulation circuit 305 and the test mode signal 319 and outputs an address (Y address (subarray specified), X address (subarray specified)).
The address scrambler 307 inputs the Y address (subarray specification) and the X address (subarray specification) and outputs a Y address 317 and a X address 318. Moreover in this embodiment, the test mode signal, the X address 317 and the Y address 318 are output to a memory 311 through the RAM interface block 309.
As described above, in a semiconductor integrated circuit disclosed by Yoshizawa, in a test circuit for one memory 311, the address modulation circuit 305 and the testing subarray specification circuit 306 are connected to the counter 304 which can generate an address in ascending and descending order and by specifying a test mode, a test pattern of address operations other than the march test and the checkerboard test which simply test in an address ascending and descending order can be generated.
However in a test of a memory, besides failures that can be detected in a read-out test to continuous addresses, there are failures that can be detected by a read-out test to discontinuous addresses. Accordingly, by performing a data read-out test of a remote address, it is possible to provide products with higher reliability. As such test method, it can be considered to perform a test by accessing from the bottom address to the top address in a memory address. For example, as shown in FIG. 4, assuming that the bottom address (=0) and the top address (=MAX) is alternately selected for a row address, if a column address is incremented for every top address, a read-out test can be sequentially performed to memory cells of the bottom address and the top address of the row address.
In this document, for at least one of row and column address, performing a test by alternately selecting the bottom address and the top address is referred to as a boundary test. For the boundary test, there are following methods shown in FIGS. 4 to 12 described later depending on the method of address selection. Moreover, the top address and the bottom address in a row and a column are collectively referred to as a boundary address. A cell having a boundary address in at least one of a row or a column address is referred to as a boundary cell. That is, the test between boundary cells is referred to as a boundary test.
The semiconductor integrated circuit disclosed by Sakamoto is able to perform a test to a plurality of memories (DRAM) with different size by the shared BIST. However, in such case, it may be the state of accessing a nonexistence address in either of the memory with smaller size. In such case, the test operation must be stopped by disabling an address access and storing a refresh signal into the memory. Therefore, in a memory with small size, the continuity of address change disappears and the boundary test of address cells cannot be performed. In order to compensate this, it is necessary to perform a test separately, thereby increasing the test time.
Moreover, in the semiconductor integrated circuit disclosed by Ida, each memory is assumed to be tested in serial although the BIST is shared. Accordingly, the test time is the total test time of each memory and there is a problem that the test time is long. Furthermore, it is not possible to perform a test that carries out only the address boundary test.
Furthermore, the semiconductor integrated circuit disclosed by Yoshizawa does not have the mechanism of sharing a BIST circuit among a plurality of memories and a BIST circuit is prepared for each memory. Therefore, to a plurality of memories with different size, it is not possible to generate a test pattern including an address cell boundary test in parallel. Moreover, the overhead of area is large.
As described above, as for Sakamoto and Ida, a circuit for generating a test pattern other than incrementing or decrementing an address is not included. We have now discovered that for this reason, when testing a plurality of memories with different size, a pattern for testing only between address cell boundaries cannot be generated and the boundary portion cannot be tested sufficiently. Moreover, even when testing between address cell boundaries that can be performed by the march test and the checkerboard test, the test time increases. Furthermore, we have also discovered that as for the technique disclosed by Yoshizawa, there is no circuit included such as an address MAX value memory circuit and an address check circuit for a memory in order to share a test circuit among the plurality of memories to test in parallel.